The present invention relates to a clock control technique and a circuit conversion technique for a semiconductor integrated circuit and specifically to a clock control technique for reducing the electric power required for the operation of a sequential circuit and a circuit conversion technique for converting a general sequential circuit to a sequential circuit capable of low-power operation. Furthermore, the present invention relates to a communication device, information reproducing device, image displaying device, and other electronic devices and electronic control devices incorporating a semiconductor integrated circuit having such a low-power sequential circuit, and a movable apparatus including such an electronic control device.
Clock control is one of the methods for realizing low-power operation of a sequential circuit. Conventional clock control techniques can be generally divided into two groups.
FIGS. 34A and 34B illustrate a general concept of a conventional clock control technique. A data control circuit 100 shown in FIG. 34A selects any one of an output of a memory element 11, whose content is updated in synchronization with supplied clock CLK, and supplied data (data input) according to data input selection signal SEL, and the selected data is input to the memory element 11. The content of the memory element 11 is updated at a rising or falling timing of supplied clock CLK. Thus, in view of the function of updating the content of the memory element 11, selection of the output of the memory element 11 by the data control circuit 100 as a new content to be stored is equivalent to no change occurring in clock CLK. Therefore, the circuit structure of FIG. 34A can be replaced with a circuit structure which includes a clock control circuit 101 as shown in FIG. 34B. The clock control circuit 101 controls clock CLK which is to be supplied to the memory element 11 according to data input selection signal SEL. The memory element 11 updates its own content in synchronization with clock CLK (for example, see Japanese Unexamined Patent Publication No. 11-149496).
FIGS. 35A and 35B illustrate a general concept of another conventional clock control technique. Referring to FIG. 35A, it is assumed that the outputs of memory elements 11a and 11b are passed through a combination circuit 12 and input to a memory element 11c. The content of the memory element 11c is updated at a rising or falling timing of synchronous clock CLK. Herein, we consider a case where the specifications of the functions of this circuit are such that “the functions of the circuit are not affected even when the contents of the memory elements are not updated for a certain period”. In this case, the circuit structure of FIG. 35A can be equivalently replaced with the circuit structure of FIG. 35B wherein the clock control circuit 101 controls supply/stop of clock CLK based on clock control signal CTL (for example, see Japanese Unexamined Patent Publication No. 8-263466).
In general, the specifications of sequential circuits are classified into (a) clock stoppable type and (b) clock unstoppable type. The circuits of type (b) are further generally classified into (b-1) circuits having feedback of the output of a memory element and (b-2) circuits not having feedback of the output of a memory element.
According to the above classification, the conventional technique shown in FIGS. 34A and 34B falls within type (b-1), and the conventional technique shown in FIGS. 35A and 35B falls within type (a). That is, the conventional technique of FIGS. 34A and 34B cannot be realized without the data control circuit 100. The conventional technique of FIGS. 35A and 35B cannot be realized without providing a stop period where the functions of the circuit are not affected even when the operation of the memory element 11c is stopped. Thus, the conventional clock control techniques require the above-described special prerequisite condition, which make clock control of the sequential circuit complicated.